The present invention relates to generating a larger magnitude output voltage from an input voltage, and more particularly, to on-chip charge pumps.
Many electronic devices require a plurality of operating voltages. However, the power supply which furnishes power to electronic devices often only have a rather limited number of different output voltages. Thus, many electronic devices include power conversion circuitry to ensure the availability of the required voltages.
In many instances, the magnitude of an input power signal must be converted to a power signal having a voltage with a higher magnitude. Devices which perform this type of power conversion are known as charge pumps. For example, if a charge pump is provided with a positive input voltage, it may generate an output voltage which is more positive than the input voltage. Alternatively, if a charge pump is provided with a negative input voltage, it may generate an output voltage which is more negative than the input voltage.
One example of an electronic device which requires a charge pump is a dynamic random access memory (DRAM) device. DRAM devices typically include a large plurality (e.g., millions) of DRAM cells arranged in one or more arrays. A typical DRAM cell 100 is illustrated in FIG. 1. The information stored in a DRAM cell 100 is written to or read from a capacitor 102. The capacitor 102 is coupled to a potential source 105 and a source 101s of a transistor 101. The transistor 101 is used to control access to the capacitor, and is itself coupled to a word line 104 via gate 101g, as well as bit line 103 via drain 101d. The DRAM cell 100 is said to store a logical 0 if the amount of charge stored within the capacitor is such that node 102a is at a potential less than a reference potential, for example, ground potential. If the amount of charge stored in the capacitor 102 is such that the potential at node 102a is greater than the reference potential, the DRAM cell 100 is said to store a logical 1, for example Vcc potential. The reference potential corresponds to the potential of a reference capacitor (not shown) having an equilibrated charge, and typically corresponds to xc2xd Vcc. Typical values for Vcc include 5.0 volts and 3.3 volts. However, there is a trend towards using smaller voltages for Vcc, since reducing the magnitude of Vcc is advantageous for reducing power consumption, thereby permitting higher density and/or higher speed DRAM devices. DRAM devices are ordinarily coupled to power line(s) having a potential of Vcc. Many portions of a DRAM device require a voltage Vpp which is greater than Vcc. The DRAM device must therefore use a charge pump to create the higher Vpp and Vccp potentials from Vcc.
FIG. 2 is an illustration of a semiconductor device 200 which includes an integrated charge pump 202. The charge pump 202 and the operational circuit 203 are coupled to a ground potential GND via ground signal line 206 and to Vcc via signal line 205. The operational circuit 203 may include a variety of circuits. If the semiconductor device 200 is a DRAM, then the operational circuit would include portions of the DRAM circuitry. The semiconductor device 200 may alternatively be any number of other devices which may require the use of a charge pump 202 to generate a higher potential from base potential.
FIG. 3 is an illustration of a simple prior art pump circuit 300. The pump circuit 300 comprises an oscillator 301 which produces a square wave (or pulse train) which swings between ground potential and Vcc. An inverter 302 may be used to condition the square wave. The oscillator 301 produces a signal having a potential Vcc during a first phase. After the signal passes through inverter 302, it arrives at node 303 having ground potential. Meanwhile, transistor 306, which has a drain coupled to a power source having a potential of Vcc, is conducting, while transistor 307 is non-conducting. Thus, node 305 has a potential somewhat lower than Vcc and charge from the power source Vcc is being stored into capacitor 304. As charge is stored in capacitor 304, the potential at node 305 increases.
During the second phase of the oscillator 301, the oscillator 301 produces a signal at ground potential, which is transformed by the inverter 302 into a signal having a potential of Vcc. This further charges capacitor 304 and further raises the voltage at node 305. As the potential at node 305 builds, transistor 306 becomes non-conducting while transistor 307 becomes conducting. This causes the charge stored in capacitor 304 to be shared with the loading capacitor 308, thereby raising the voltage at the output terminal 309. During subsequent clock cycles, the charge stored in capacitor 304 during the first phase of the oscillator is transferred to the loading capacitor 308 during the second phase, resulting in a elevated voltage Vccp at the output terminal 309.
The prior art pump circuit 300 is dependent upon the capacitor 304 to generate the boosted voltage Vccp. This limits the operating frequency of the prior art pump circuit to the rate at which the capacitor 304 can be charged and discharged. As semiconductor devices such as DRAMs increase in frequency, it becomes increasingly difficult to charge and discharge the capacitor 304 at a corresponding higher rate. Thus, the prior art pump circuit 300 is unsuitable for use in high speed memory devices. Accordingly, there is a need for an apparatus and a method for a charge pump which is suitable for operation in high speed and/or low powered semiconductor devices.
The present invention is directed at an on-chip charge pump capable of supplying the boosted voltage required in a high speed semiconductor device such as a high speed dynamic random access memory (DRAM). The charge pump of the present invention is powered by the flyback effect of an inductor. The use of an inductor""s flyback effect for the purpose of generating a boosted voltage is known. For example, the flyback effect is routinely used to generate the 10 kV high anode voltage in televisions and other cathode ray tube devices. However, semiconductor devices have traditionally used capacitor based charge pumps. In the present invention, a flyback based charge pump and its associated inductor are integrated into the semiconductor device. In the high speed semiconductor device, such as a DRAM, an inductor based charge pump may be operated at higher frequency than a traditional capacitor based charge pump.